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MC100EL14 5V ECL 1:5 Clock Distribution Chip
The MC100EL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The EL14 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pulldown resistor) the SEL pin will select the differential clock input. The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input.
Features
20 100EL14 AWLYYWWG
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SOIC-20L DW SUFFIX CASE 751D
MARKING DIAGRAM
* * * * * *
50 ps Output-to-Output Skew Synchronous Enable/Disable Multiplexed Clock Input The 100 Series Contains Temperature Compensation PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V Q Output will Default LOW with Inputs Open or at VEE on Inverted Inputs Pb-Free Packages are Available*
1 A WL YY WW G
* * Internal Input Pull-down Resistors on All Inputs, Pull-up Resistors *
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
*For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
October, 2006 - Rev. 7
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Publication Order Number: MC100EL14/D
MC100EL14
VCC 20 EN VCC 19 18 NC SCLK CLK CLK VBB 17 16 15 10 D Q 14 13 SEL 12 VEE 11
Table 1. PIN DESCRIPTION
PIN CLK, CLK SCLK EN SEL Q0-4, Q0-4 FUNCTION ECL Diff Clock Inputs ECL Scan Clock Input ECL Sync Enable ECL Clock Select Input ECL Diff Clock Outputs Reference Voltage Output Positive Supply Negative Supply No Connect
1 Q0
2 Q0
3 Q1
4 Q1
5 Q2
6 Q2
7 Q3
8 Q3
9 Q4
10 Q4
VBB VCC VEE NC
* All VCC pins are tied together on the die. Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Figure 1. Logic Diagram and Pinout Assignment
Table 2. FUNCTION TABLE
CLK* L H X X X SCLK* X X L H X SEL* L L H H X EN* L L L L H Q L H L H L (Note )
1. On next negative transition of CLK or SCLK **Pins will default low when left open.
Table 3. ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charge Device Model Value 75 kW 75 kW > 2 kV > 200 V > 4 kV Level 1 Oxygen Index: 28 to 34 UL 94 V-0 @ 0.125 in 303 Devices
Moisture Sensitivity (Note 2) Flammability Rating Transistor Count Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
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MC100EL14
Table 4. MAXIMUM RATINGS
Symbol VCC VEE VI Iout IBB TA Tstg qJA qJC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm Standard Board <2 to 3 sec @ 248C <2 to 3 sec @ 260C SOIC-20L SOIC-20L SOIC-20L Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 8 -8 6 -6 50 100 0.5 -40 to +85 -65 to +150 90 60 30 to 35 265 265 Unit V V V V mA mA mA C C C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
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MC100EL14
Table 5. 100EL SERIES PECL DC CHARACTERISTICS VCC = 5.0 V; VEE = 0.0 V (Note 3)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 4) Output LOW Voltage (Note 4) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Common Mode Range (Differential Configuration) (Note 5) VPP < 500 mV VPP 500 mV Input HIGH Current Input LOW Current 0.5 3915 3170 3835 3190 3.62 Min Typ 32 3995 3305 Max 40 4120 3445 4120 3525 3.74 3975 3190 3835 3190 3.62 Min 25C Typ 32 4045 3295 Max 40 4120 3380 4120 3525 3.74 3975 3190 3835 3190 3.62 Min 85C Typ 34 4050 3295 Max 42 4120 3380 4120 3525 3.74 Unit mA mV mV mV mV V V 1.3 1.5 4.6 4.6 150 0.5 1.2 1.4 4.6 4.6 150 0.5 1.2 1.4 4.6 4.6 150 mA mA
IIH IIL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. Input and output parameters vary 1:1 with VCC.VEE can vary +0.8 V / -0.5 V. 4. Outputs are terminated through a 50 W resistor to VCC - 2.0 V. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC.The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPP(min) and 1 V.
Table 6. 100EL SERIES NECL DC CHARACTERISTICSVCC = 0.0 V; VEE = -5.0 V (Note 6)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 7) Output LOW Voltage (Note 7) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Common Mode Range (Differential Configuration) (Note 8) VPP < 500 mV VPP 500 mV Input HIGH Current Input LOW Current 0.5 -1085 -1830 -1165 -1810 -1.38 Min Typ 32 -1005 -1695 Max 40 -880 -1555 -880 -1475 -1.26 -1025 -1810 -1165 -1810 -1.38 Min 25C Typ 32 -955 -1705 Max 40 -880 -1620 -880 -1475 -1.26 -1025 -1810 -1165 -1810 -1.38 Min 85C Typ 34 -955 -1705 Max 42 -880 -1620 -880 -1475 -1.26 Unit mA mV mV mV mV V V -3.7 -3.5 -0.4 -0.4 150 0.5 -3.8 -3.6 -0.4 -0.4 150 0.5 -3.8 -3.6 -0.4 -0.4 150 mA mA
IIH IIL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. Input and output parameters vary 1:1 with VCC.VEE can vary +0.8 V / -0.5 V. 7. Outputs are terminated through a 50 W resistor to VCC - 2.0 V. 8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC.The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPP(min)and 1 V.
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MC100EL14
Table 7. AC CHARACTERISTICS VCC = 5.0 V; VEE = 0.0 V or VCC = 0.0 V; VEE = -5.0 V (Note 9)
-40C Symbol fmax tPLH tPHL tSKEW tJITTER tS tH VPP tr tf Characteristic Maximum Toggle Frequency (See Figure 2, fMAX/Jitter) Prop Delay CLK to Q (Diff) CLK to Q (SE) SCLK to Q 520 470 470 Min Typ 1 720 770 770 200 50 1 0 250 150 230 1000 500 0 250 150 230 1 -133 140 1000 500 0 250 150 230 1000 500 580 530 530 Max Min 25C Typ 1 680 680 680 780 830 830 200 50 1 630 580 580 Max Min 85C Typ 1 830 880 880 200 50 Max Unit GHz ps
Part-to-Part Skew Within-Device Skew (Note 10) Random Clock Jitter (RMS) @ 1 GHz (See Figure 2, fMAX/Jitter) Setup Time EN Hold Time EN Input Swing (Note 11) Output Rise/Fall Times Q (20% - 80%)
ps ps ps ps mV ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. VEE can vary +0.8 V / -0.5 V. Outputs are terminated through a 50 W resistor to VCC - 2.0 V. 10. Skews are specified for identical LOW-to-HIGH or HIGH-to-LOW transitions. 11. VPP(min) is the minimum input swing for which AC parameters guaranteed. The device has a DC gain of 40. 800 700 600 500 400 0.5 300 200 200 2.0
Jitter
1.0
400
600
800 FIN (MHz)
1000
1200
0 1400
Figure 2. Output Voltage Amplitude / RMS Jitter vs. Input Frequency at Ambient Temperature (Typical)
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JITTEROUT ps (RMS)
VOUTPP VOUTPP (mV)
1.5
MC100EL14
Q Driver Device Q Zo = 50 W 50 W 50 W D Zo = 50 W D Receiver Device
VTT VTT = VCC - 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
ORDERING INFORMATION4
Device MC100EL14DW MC100EL14DWG MC100EL14DWR2 MC100EL14DWR2G Package SOIC-20L SOIC-20L (Pb-Free) SOIC-20L SOIC-20L (Pb-Free) Shipping 38 Units / Rail 38 Units / Rail 1000 / Tape & Reel 1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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MC100EL14
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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MC100EL14
PACKAGE DIMENSIONS
SO-20 WB CASE 751D-05 ISSUE G
D
A
11 X 45 _
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1 10
20X
B 0.25
M
B TA
S
B
S
A e
SEATING PLANE
h
18X
A1
T
C
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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L
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MC100EL14/D

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